1. Field of the Invention
The invention of this application relates in general to digital logic circuitry and, in particular, to asynchronously timed digital flip-flops which incorporate special output circuits to reject false outputs.
2. Description of the Prior Art
In digital systems it is desirable to use bi-stable memory elements which change state in response to the application of a binary input signal. This type of element is called a flip-flop. A common elementary form of the flip-flop is the "set-reset" flip-flop in which a binary input signal applied to one input called the set input causes the flip-flop to assume the set state and a corresponding binary input signal applied to the reset input causes the flip-flop to assume the reset state.
Set-reset flip-flops are useful in many of the components of digital systems. They form the basic building blocks for more complex, notorial and sequential logic circuits such as counters, multiplexers, memories, shift registers, and others.
Logic circuitry commonly shows the set-reset flip-flop in an elementary form as a pair of coincident gates cross coupled so that the logic level at the output of one gate feeds back to the input of the other gate to latch the flip-flop in a stable state. Application of the appropriate input logic signal causes a change at a gate output and the cross coupling of this output back to the input of the other gate will cause the flip-flop to assume its other stable state. Thus the flip-flop can be set and reset. The elementary form of the set-reset flip-flop can consist of cross coupled NOR gates or cross coupled NAND gates. The choice of configuration depends on whether logic 1 or logic 0 is the active level of the input exitation of the flip-flop.
When flip-flops are used in logic designs which include the use of asynchronous timing signals, a troublesome problem can occur when the flip-flop assumes a quasi-stable state in which its outputs are at a logically indeterminant level between a logic 0 and a logic 1. This indeterminant level derives from the fact that the input to output transfer characteristic of any inverting type gate must include one particular point where the input and output levels are identically equal. It then follows that when coincident gates having transfer characteristics of this type are cross coupled to form a basic flip-flop element, it is possible to have an operating point where the inputs and the outputs of each of the cross coupled coincident gates will all be at a logically indeterminant level midway between the valid level for a logical 0 and the valid level for a logical 1. This logically indeterminant level is the threshold level of the gate. The problems associated with this indeterminant state are normally not encountered in timed logic systems because correct timing design insures that inputs to the set or reset cross coupled coincident gate flip-flop are of sufficient time duration to insure that inputs are forced to a valid logical 0 or logical 1 level. The problem emerges, however, in asynchronously timed systems in which the exact time duration of the input signals which will determine whether the coincident gate flip-flop gate is set or reset often cannot be predicted or controlled. As the detailed description which follows will show, asynchronous timing signals applied to a logic circuit which includes a cross coupled coincident gate flip-flop can result in a situation where one input signal which tends to force the flip-flop to the set state is in a "race" with another input signal which tends to have the opposing effect of maintaining the flip-flop in the reset state. When the degree of time asynchronism is slight, it is possible for the coincident gate flip-flop to assume the indeterminant state described above and thus generate a "false" output.
Another aspect of the problem associated with the generation of false outputs is that since all inverting coincident gates have similar transfer characteristics, it is possible for the logically indeterminant level midway between a valid logic 0 and a valid logic 1 to propagate through a series of interconnected gates in a logic system. This problem is accentuated in logic circuits implemented using monolithic integrated circuits because the characteristics of the devices forming coincident gates tend to closely match each other so that gate thresholds are essentially identical. Thus an input signal at the threshold level tends to produce an output signal at the threshold level which then creates a repetitive situation at the next gate in the sequential chain.